It has long been recognized that analog to digital conversion, i.e., the production of a binary number having a value related to an analog voltage input, presents a complex and challenging problem to circuit designers. Some A/D converters have been designed employing a successive approximation scheme. In such a device, a binary number generator is coupled to a digital-to-analog (D/A) converter (a relatively simple device). The output of the D/A converter is coupled to a first input of a comparator, and the input analog voltage is coupled to a second input of the comparator. The binary number is changed in value until a threshold value is determined at which the output of the D/A converter equals the input voltage, to within a suitable resolution. The binary number which the binary number generator is producing at that time is then deemed to be a digital equivalent of the input analog voltage.
A disadvantage of this type of device is that a series of binary approximations, which may consume a large number of system clock cycles, is required for finding the binary threshold value. Accordingly, this type of A/D converter is undesirably slow in operation.
To alleviate this problem of excessive time for producing a digital output, parallel flash A/D converter circuits have been employed. In a flash A/D circuit, a binary digital output can be produced in a single clock cycle. Conventional flash A/D converters have employed resistor ladder networks in which a series of resistors, each having the same value, is connected between high and low reference voltage sources. Nodes between the resistors provide reference voltages. Each node is connected to a stage, typically including a comparator, which produces an output signal whose value depends on whether or not the input voltage exceeds the corresponding reference voltage. Outputs of the stages are decoded to produce a binary number having a value related to the value of the analog input voltage.
It will be seen that, in general, a trade-off between circuit size and speed exists in A/D converters. The conventional successive approximation A/D converter is relatively small in size, but requires many clock cycles to provide a successive approximation digital equivalent of the analog input voltage. By contrast, the flash A/D converter described above produces an output in only one clock cycle, but requires a resistor ladder network having 2.sup.n +1 resistors to produce 2.sup.n nodes, 2.sup.n stages, each of which may include a comparator, and a decoding network which, if implemented as a programmable logic array, has 2.sup.n inputs and n outputs, and thereby requires a comparably large array of solid state devices for implementing the required interconnections. Thus there is a problem that an undesirably large circuit, or an undesirably large integrated circuit, has been required for producing a flash A/D converter.